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GSM Half-Rate Speech Codec: Bit Exactness versus DSP-Architecture

Authors:
Fingscheidt, T. ,  Wiechers, T. ,  Delfs, E.
Book Title:
DSP Deutschland '95
Organization:
n.n.
Pages:
p.p. 203-207
Address:
Munich, Germany
Date:
Sep. 1995
Language:
English

Abstract

The European Telecommunications Standards Institute (ETSI) has specified the GSM Half-Rate Codec with a bit rate of 5.6 kbit/s in January 1995. The specification requires bit exactness which imposes strict constraints on an implementation using any fixed point DSP. To investigate the matching of the GSM Half-Rate Codec algorithm to a given DSP, the most frequently used "basic mathematical operations" in the algorithm are examined. Their complexities on different DSPs strongly depend on the architecture (saturation logic e.g.), but also vary with the range of the numbers they are working on. The paper first deals with architectural aspects and bit exactness requirements regarding the very frequently used shift operations as well as the multiply-accumulate (MAC) instruction. Afterwards an efficient input value dependent solution for shift routines is specified adapted to the GSM Half-Rate Codec. Furthermore, low complexity implementation possibilities of the MAC instruction in some time critical parts of the algorithm are stated for DSPs not providing the saturation requirements as specified by ETSI. To resume the methods of efficiency enhancement, a complexity estimate is done assuming different versions of a fictional DSP. Finally, a bit exact implementation using the NECµ PD77018 DSP will be discussed as an example. Although this DSP differs from the "ideal" one, an efficient implementation can be obtained by a consequent realization of the previously discussed complexity reduction aspects.

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