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Diplom-Vortrag: Design of an LDPC Channel Decoder for Satellite Communication Based on the GMR Standard

Thorsten Riechers
30. Mai 2011
11:00 Uhr
Hörsaal 4G IKS

In densely populated areas, the terrestrial, cellular mobile phone network based on the GSM technology is one of the predominant communication facilities. However, terrestrial networks are often limited to regions providing a certain communication infrastructure. An alternative to terrestrial communication networks is given by satellite communication systems. Satellites are employed for long distance connections and provide communication services to regions, where terrestrial networks are not feasible.  

Analog to the GSM specification, the GMR-1 3G standard specifies communication services over geostationary satellites, such as voice calls, fax and Internet-based data services. Signals propagating from and to the satellite have to travel large distances and the communication link is exposed to various noise sources, e.g., the used electronic components, radiation from space, weather conditions as well as the atmosphere. Hence, it is inevitable that the signal contains errors after traveling from the satellite to the Earth terminal antenna or vice versa. This enforces the need for effective channel codes, which can be used to correct errors in the received signal, such as turbo codes and LDPC codes. LDPC codes were initially found by Robert Gallager in 1962, first remained unattended and finally were rediscovered in the 1990s. They have advantages over turbo codes, but are also computationally more expensive.  

The thesis comprises the development of an LDPC decoder to efficiently correct erroneous received signals. The decoder should fulfill the requirement profile of a base station for satellite communication networks complying with the GMR-1 3G standard. The performance goal is that it provides the capability of decoding up to 100 LDPC encoded data transfers simultaneously in real time. This requires that the LDPC decoder achieves a peak throughput of 44.4 Mbit/s. For the realization of the LDPC decoder, an alternative programmable hardware is examined, which is a GPU from Nvidia. In the thesis, realizations and approximations of the standard decoding algorithm for LDPC codes are discussed. Furthermore, two approaches for an implementation on a GPU are analysed and a decoder design is presented.

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