Implementation Aspects of the GSM Half-Rate Speech Codec

Authors:

Fingscheidt, T. ,  Wiechers, T. ,  Delfs, E.

Book Title:

Proceedings of European Conference on Speech Communication and Technology (EUROSPEECH)

Organization:

ESCA

Pages:

p.p. 723-726

Address:

Madrid, Spain

Date:

Sep. 1995

Language:

English

Abstract

In this paper the GSM Half-Rate Speech Codec is examined with respect to implementation complexity taking the bit exactness requirements as well as differences in DSP-architectures into consideration. While the ETSI codec specification assumes some "ideal DSP" with a certain architecture, it turns out that the implementation on a real-world DSP could require about 50 MIPS. The computational load can be reduced by minor modifications of the DSP instruction set (appropriate saturation logic and barrel shifter) down to 25 MIPS. However, by exploiting detailed knowledge of the codec algorithm, a processor load of less than 25 MIPS can be achieved too, even if the DSP does not provide the required saturation logic. This is shown by way of example, using a single NECµ PD77018 DSP for a full duplex real time implementation. The potential for complexity reduction is discussed.

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